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  SiC Processing

 

 
Polycrystalline silicon carbide (Poly-SiC) has been surface micromachined using two methods:
  • Polysilicon sacrificial layer using KOH as a release etchant
  • SiO2 sacrificial layer using HF as a release etchant.

A single-mask surface micromachining process using the underlying polysilicon film as the sacrificial layer as been used to fabricate poly-SiC devices as shown in the process flow below. The oxide layer underneath the polysilicon film is used for electrical isolation of substrate and also protects the silicon substrate during the final release step in KOH. After growth of the poly-SiC on polysilicon, a 5000Å-thick aluminum masking layer is deposited by sputtering. Then, the aluminum layer is defined and patterned using conventional photolithography and wet-etching, respectively. Next, with the patterned aluminum layer as the etch-mask, poly-SiC microstructures are defined by reactive-ion-etching in a CHF3/O2 (97%/3%) mixture. The etch is reasonably anisotropic with an etch rate of approximately 400Å/min. After etching, the aluminum mask is removed using HF. Finally, the poly-SiC microstructures are released by etching the polysilicon sacrificial layer in 40 wt% KOH at 40oC; the etch rate is approximately 6 µm/hr. The etching time is controlled so that the polysilicon sacrificial layer is etched from everywhere but the anchor regions underneath the poly-SiC devices.

Process Flow


Film growth and
patterning

 

 

RIE etching of poly-SiC

 

Release in KOH

Free-standing lateral resonant structures have also been fabricated from poly-SiC grown on SiO2 using a single mask surface micromachining process. Again, reactive ion etching in a CHF3/O2 plasma was used to pattern the poly-SiC films. Sputter-deposited aluminum was used as the etch mask. Free standing poly-SiC structures were released by etching the SiO2 sacrificial layer in HF. The reasons for processing with an oxide sacrificial layer include:

  • CMOS compatible release etchant (HF) which does not attack Si
  • Release layer provides electrical isolation between electrostatic device elements.
  • Similar to standard polysilicon surface micromachining as shown below.

Process Flow


Film growth and
patterning

 

RIE etching of poly-SiC

 


 

Release in HF

Devices with lateral dimensions as large as 500 µm have been fabricated. Within these dimensions, residual stress induced deformations have not been noticeable in the poly-SiC micromechanical parts like those shown below.

Overview of Poly-SiC
Device Structure
Comb Region Close-up

 

 
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